Performance analysis of flip-flops at near-threshold voltage operation - Liu, Shutong (2019)
With the rise of the Internet of Things and 5G, the increase of embedded and portable devices is limited by the battery capacity, low power consumption has become the biggest demand for electronic product design in recent years. Among various circuits, the D flip- flop is the most important one in the sequential circuit. The design of the DFF greatly affects the overall power consumption. The main purpose of this dissertation is to simulate the four D flip-flop circuits at near- threshold voltage using Cadence software (TSMC 40nm process) to compare their power consumption, delay and timing parameters. Firstly, starting from the power consumption of digital circuits, the low-power technologies in various stages of existing circuit design are introduced. Two traditional D flip-flop designs and two D flip-flop designs proposed in recent years have been selected. The four circuits are: Transmission Gate Flip-flop, Ture Single-phase Clock Edge-Triggered Register, Static Contention-Free Single-Phase-Clocked Flip-Flop and Enhanced mC2MOS Flip-flop. Then, according to various physical effects appearing in the near-threshold region, the corresponding simulation experiment design is carried out, and the adverse effects are eliminated as much as possible to make the overall performance of the circuit better. The power consumption of the four circuits was simulated at a process angle of TT/25°C with a supply voltage of 0.6V; The CLK-Q delay, set-up time and hold time were then measured at three process angles TT/25°C, FF/100°C, SS/0°C. In addition to displaying the simulated waveforms, the corresponding bar and scatter plots are given to facilitate comparison. The simulation data section includes an analysis of the cause of the distortion in the circuit design in which the distortion waveform appears.