Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster

• Main Authors: Moorthy, Pradeep, Kapre, Nachiket
• 其他作者: School of Computer Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2015
• 主題: Computer Science and Engineering
• 在線閱讀: https://hdl.handle.net/10356/83649; http://hdl.handle.net/10220/39205

Commodity SoCs with hybrid architectures that combine CPUs with programmable FPGA fabric such as the Xilinx Zynq SoC have become a competitive energy-efficient platform for addressing irregular parallelism in graph problems. In this paper, we prototype a 32-node cluster composed from these Zynq SoC...