Ultra-low power SRAM and SRAM based PUF design - Lu, Lu (2019)
With the recent development of portable devices and wearable technology, the requirements of long battery life-time, ultra-low power consumption and low cost in system-on-a-chip (SoC) are becoming increasingly significant. However, the aggressive CMOS technology which integrates with more devices and larger capacitor cache cause high power density. As a crucial approach to meet the ultra-low-power and energy usage, a supply voltage scaling technique has been commonly employed. The power consumption is being effectively suppressed with optimized energy efficiency under near- / sub-threshold voltage region. Meanwhile, static-random-access-memory (SRAM) designs are also facing some challenges when it comes for voltage scaling. In conventional 6T SRAMs, the minimum operating voltage is limited by the conflicting requirements from the ability to write and read stably. In addition, operating SRAMs in the near- or sub-threshold voltage regions have significantly degraded Ion-to-Ioff ratios and exponentially increased device variations, which deteriorates various SRAM design parameters, like read margin, static noise margin and write ability, etc.