Siek, L., Palaniappan, A. R., & Engineering, S. o. E. a. E. (2018). Wide-input dynamic range 1 MHz clock ultra-low supply flip-flop.
استشهاد بنمط شيكاغوSiek, Liter, Arjun Ramaswami Palaniappan, و School of Electrical and Electronic Engineering. Wide-input Dynamic Range 1 MHz Clock Ultra-low Supply Flip-flop. 2018.
MLA استشهادSiek, Liter, Arjun Ramaswami Palaniappan, و School of Electrical and Electronic Engineering. Wide-input Dynamic Range 1 MHz Clock Ultra-low Supply Flip-flop. 2018.
تحذير: قد لا تكون هذه الاستشهادات دائما دقيقة بنسبة 100%.