APA引文

Siek, L., Palaniappan, A. R., & Engineering, S. o. E. a. E. (2018). Wide-input dynamic range 1 MHz clock ultra-low supply flip-flop.

Chicago Style Citation

Siek, Liter, Arjun Ramaswami Palaniappan, and School of Electrical and Electronic Engineering. Wide-input Dynamic Range 1 MHz Clock Ultra-low Supply Flip-flop. 2018.

MLA引文

Siek, Liter, Arjun Ramaswami Palaniappan, and School of Electrical and Electronic Engineering. Wide-input Dynamic Range 1 MHz Clock Ultra-low Supply Flip-flop. 2018.