APA引文

Low, J. Y. S., Chang, C. H., & Engineering, S. o. E. a. E. (2013). A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS.

Chicago Style Citation

Low, Jeremy Yung Shern, Chip Hong Chang, and School of Electrical and Electronic Engineering. A VLSI Efficient Programmable Power-of-two Scaler for 2n-1, 2n,2n+1 RNS. 2013.

MLA引文

Low, Jeremy Yung Shern, Chip Hong Chang, and School of Electrical and Electronic Engineering. A VLSI Efficient Programmable Power-of-two Scaler for 2n-1, 2n,2n+1 RNS. 2013.