Tan, Y. S., Yeo, K. S., Boon, C. C., Do, M. A., & Engineering, S. o. E. a. E. (2013). Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit.

Tan, Yung Sern, Kiat Seng Yeo, Chirn Chye Boon, Manh Anh Do, and School of Electrical and Electronic Engineering. Design of a Hysteresis Frequency Lock Detector for Dual-loops Clock and Data Recovery Circuit. 2013.

Tan, Yung Sern, et al. Design of a Hysteresis Frequency Lock Detector for Dual-loops Clock and Data Recovery Circuit. 2013.