APA引文

HO, C. S., KARUNASIRI, R. P. G., CHUA, S. J., PEY, K. L., LEE, K. H., & ENGINEERING, E. (2012). Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices.

Chicago Style Citation

HO, CHAW SING, R. P. G. KARUNASIRI, SOO JIN CHUA, KIN LEONG PEY, KONG HEAN LEE, and ELECTRICAL ENGINEERING. Cmos Gate Architecture for Integration of Salicide Process in Sub 0.1. .muM Devices. 2012.

MLA引文

HO, CHAW SING, et al. Cmos Gate Architecture for Integration of Salicide Process in Sub 0.1. .muM Devices. 2012.