A formal framework for modeling and validating Simulink diagrams
Simulink has been widely used in industry to model and simulate embedded systems. With the increasing usage of embedded systems in real-time safety-critical situations, Simulink becomes deficient to analyze (timing) requirements with high-level assurance. In this article, we apply Timed Interval Cal...
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| Main Authors: | , , |
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| 格式: | text |
| 語言: | English |
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Institutional Knowledge at Singapore Management University
2009
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| 在線閱讀: | https://ink.library.smu.edu.sg/sis_research/5037 https://ink.library.smu.edu.sg/context/sis_research/article/6040/viewcontent/Chen2009_Article_AFormalFrameworkForModelingAnd.pdf |
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| 總結: | Simulink has been widely used in industry to model and simulate embedded systems. With the increasing usage of embedded systems in real-time safety-critical situations, Simulink becomes deficient to analyze (timing) requirements with high-level assurance. In this article, we apply Timed Interval Calculus (TIC), a realtime specification language, to complement Simulink with TIC formal verification capability. We elaborately construct TIC library functions to model Simulink library blocks which are used to compose Simulink diagrams. Next, Simulink diagrams are automatically transformed into TIC models which preserve functional and timing aspects. Important requirements such as timing bounded liveness can be precisely specified in TIC for whole diagrams or some components. Lastly, validation of TIC models can be rigorously conducted with a high degree of automation using a generic theorem prover. Our framework can enlarge the design space by representing environment properties to open systems, and handle complex diagrams as the analysis of continuous and discrete behavior is supported. |
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