CIM-Spin: a scalable CMOS annealing processor with digital in-memory spin operators and register spins for combinatorial optimization problems

by Su, Yuqi, Kim, Hyunjoon, Kim, Bongjin
Published 2022

A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems

by Su, Yuqi, Mu, Junjie, Kim, Hyunjoon, Kim, Bongjin
Published 2022

A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter

by Chen, Qian, Liang, Yuan, Kim, Bongjin, Boon, Chirn Chye
Published 2020

Reconfigurable 2T2R ReRAM architecture for versatile data storage and computing in-memory

by Chen, Yuzong, Lu, Lu, Kim, Bongjin, Kim, Tony Tae-Hyoung
Published 2022

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits

by Park, Gyusung, Kim, Minsu, Kim, Chris H., Kim, Bongjin, Reddy, Vijay
Published 2019

A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks

by Yu, Chengshuo, Yoo, Taegeun, Chai, Kevin Tshun Chuan, Kim, Tony Tae-Hyoung, Kim, Bongjin
Published 2022

A time-domain wavefront computing accelerator with a 32 × 32 reconfigurable PE array

by Yu, Chengshuo, Mu, Junjie, Su, Yuqi, Chai, Kevin Tshun Chuan, Kim, Tony Tae-Hyoung, Kim, Bongjin
Published 2023

Co-optimization of algorithm and hardware for energy and area efficient binary neural network

by Ng, Samuel Ming Ern
Published 2018

Reconfigurable digital compute-in-memory circuit designs for solving combinatorial optimization problems

by Lyu,Shicheng
Published 2020

Machine learning circuit design for processing neural networks in image sensor

by Nabeel Najeeb Kassim
Published 2020