Retraining mechanism for on-line peer-to-peer traffic classification

by Zarei, R., Monemi, A., Marsono, M. N.
Published 2013

An FPGA hardware architecture of Nilsimsa fingerprinting algorithm

by Monemi, A., Mohamed, M. A., Marsono, Muhammad Nadzir
Published 2011

Virtual channel and switch allocation for low latency network-on-chip routers

by Monemi, A., Ooi, C. Y., Marsono, M. N.
Published 2015

Parameterizable decision tree classifier on NETFPGA

by Monemi, A., Zarei, R., Marsono, M. N., Khalil-Hani, M.
Published 2013

Improved flow control for minimal fully adaptive routing in 2D mesh NoC

by Monemi, A., Ooi, C. Y., Marsono, M. N., Palesi, M.
Published 2016

Ping-lock round robin arbiter

by Monemi, A., Ooi, C. Y., Palesi, M., Marsono, M. N.
Published 2017

ProNoC: a low latency network-on-chip based many-core system-on-chip prototyping platform

by Monemi, A., Tang, J. W., Palesi, M., Marsono, M. N.
Published 2017