Wide-input dynamic range 1 MHz clock ultra-low supply flip-flop

by Siek, Liter, Palaniappan, Arjun Ramaswami
Published 2018

A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS

by Palaniappan, Arjun Ramaswami, Siek, Liter
Published 2021

A TDC-less all-digital phase locked loop for medical implant applications

by Palaniappan, Arjun Ramaswami, Siek, Liter
Published 2021

A 0.0186 mm2, 0.65 V supply, 9.53 ps RMS jitter all-digital PLL for medical implants

by Palaniappan, Arjun Ramaswami, Siek, Liter
Published 2021