A 0.0186 mm2, 0.65 V supply, 9.53 ps RMS jitter all-digital PLL for medical implants

• Main Authors: Palaniappan, Arjun Ramaswami, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; All-Digital Phase Locked Loop (ADPLL); Bootstrapped
• Online Access: https://hdl.handle.net/10356/152113
• Institution: Nanyang Technological University

An ultra-low area and low power all-digital phase locked loop (ADPLL) has been designed for use in biomedical implant applications. The ADPLL can provide a differential output signal with a frequency range from 330 MHz to 470 MHz while operating at a supply of 0.65 V. The proposed ADPLL eliminates t...