A 0.0186 mm2, 0.65 V supply, 9.53 ps RMS jitter all-digital PLL for medical implants

• Main Authors: Palaniappan, Arjun Ramaswami, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; All-Digital Phase Locked Loop (ADPLL); Bootstrapped
• Online Access: https://hdl.handle.net/10356/152113
• Institution: Nanyang Technological University

An ultra-low area and low power all-digital phase locked loop (ADPLL) has been designed for use in biomedical implant applications. The ADPLL can provide a differential output signal with a frequency range from 330 MHz to 470 MHz while operating at a supply of 0.65 V. The proposed ADPLL eliminates the use of LC oscillator and time-to-digital converter for achieving an ultra-low area implementation suitable for biomedical implants. Techniques such as capacitive boosting and fractional capacitor tuning have been applied to the ring oscillator of the proposed ADPLL for achieving good jitter performance. The proposed ADPLL consumes a power of 270.5 μW at 0.65 V supply while running at an output frequency of 400 MHz and exhibits an rms jitter of 9.53 ps. The ADPLL has been designed in 40 nm CMOS and occupies an active area of only 0.0186 mm 2 .