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SI, Yuanjie
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SI, Yuanjie
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SI, Yuanjie
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1
Improving model checking stateful timed CSP with non-zenoness through clock-symmetry reduction
by
SI
,
Yuanjie
,
SUN, Jun
,
LIU, Yang
,
WANG, Ting
Published 2013
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2
Combining model checking and testing with an application to reliability prediction and distribution
by
GUI, Lin
,
SUN, Jun
,
LIU, Yang
,
SI
,
Yuanjie
,
DONG, Jin Song
,
WANG, Xinyu
Published 2013
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3
A systematic study on explicit-state non-zenoness checking for timed automata
by
WANG, Ting
,
SUN, Jun
,
WANG, Xinyu
,
LIU, Yang
,
SI
,
Yuanjie
,
DONG, Jin Song
,
YANG, Xiaohu
,
LI, Xiaohong
Published 2015
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