#TITLE_ALTERNATIVE#

• Main Author: BAGJA NUGRAHA (NIM 13204212), ASEP
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/10032
• Institution: Institut Teknologi Bandung

Channel estimation attempts to track the respons frequency of channel by periodically sending pilot and preamble symbol which enable it to characterize the channel at that time. The pilot and preamble symbol is used as reference for channel estimation. Then the result of channel estimation can be used by equalizer to correct the received data so that they can be decoded properly.<p> <br /> <br /> <br /> This final project implements channel estimator and equalizer, specialized for WIMAX 802.16-2004 receiver. Channel estimation is implemented based on Least Square algorithm (LS), while equalizer use minimum mean square error (MMSE) algorithm. In order to increase performance, we use interpolation to calculate the channel respons on subcarriers which are not pilot subcarriers.<p> <br /> <br /> <br /> In order to reduce hardware complexity than using floating point number, functional calculation is modeled using fixed point model. Multiplication uses Booth algorithm for complex number in order to reduce the number of partial product. Division uses cordic algorithm since for complex number this algorithm is more efficient than direct calculation using addition, multiplication and division. The design is intended until RTL level which must be synthesized on FPGA.<p> <br /> <br /> <br /> Verifications of the designed channel estimator and equalizer are based on modular test, integrated test and verification test on FPGA board. In modular test, output of fixed point model on MATLAB is compared with the output of RTL design. In integrated test, the design is integrated into complete WIMAX receiver to repair the received data so that it can be decoded properly. The last test is done on FPGA board using Signal Tap. The functionality of the design has been proved by comparing output of Signal Tap on Quartus II and output of ModelSim simulator. The tests show that our design works properly on all kind of verification. The FPGA prototyping has been done on Altera DE2 Cyclone II EP2C35F672C6N and Quartus II 7.2 software. The desain is able to work at a frequency of 77.66 MHz. The required logic element and memory bit are respectively, 18814 logic element and 126976 memory bits.