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In this final project, a frequency synthesizer for WiMAX subscriber-station is presented. Based on a phase-locked loop, the synthesizer can provide various channel selection to cover 1,75 MHz channel bandwidth or its multiply. A programmable divider is proposed using traditional fractional-n or usua...

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Main Author: BASKORO (NIM 13204005), FARID
Format: Final Project
Language:Indonesia
Online Access:https://digilib.itb.ac.id/gdl/view/10409
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Institution: Institut Teknologi Bandung
Language: Indonesia
id id-itb.:10409
spelling id-itb.:104092017-09-27T10:18:44Z#TITLE_ALTERNATIVE# BASKORO (NIM 13204005), FARID Indonesia Final Project INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/10409 In this final project, a frequency synthesizer for WiMAX subscriber-station is presented. Based on a phase-locked loop, the synthesizer can provide various channel selection to cover 1,75 MHz channel bandwidth or its multiply. A programmable divider is proposed using traditional fractional-n or usually called pulse-swallow divider scheme.<p> <br /> <br /> <br /> <br /> <br /> Phase noise of a PLL synthesizer is a major one-chip solution design consideration. A phase noise requirement is firstly derived from spectral emission specification on the IEEE 802.16-2004 standard. Then the frequency synthesizer's components are designed to fulfill those requirements. The derived phase noise requirement was on five point references.<p> <br /> <br /> <br /> <br /> <br /> The frequency synthesizer consists of PFD, Charge-pump, Loop filter, VCO, and Divider circuit. The VCO is using negative-Gm oscillator topology. This oscillator does not need any extra circuitry to maintain its amplitude. The capacitance which is usually connected in parallel with the inductance to form the LC-tank is divided into 2 similar varactor. The control voltage to the varactor was single ended due to simplicity design on the charge-pump and loop filter.<p> <br /> <br /> <br /> <br /> <br /> The frequency synthesizer was simulated using RF transistor available in AMS 0.35 um technology kit. The VCO control voltage can be tuned between 1,2-5 Volt. The VCO output frequency at 3.5 volt control voltage is 2.338 GHz. The VCO output is a differential signal with voltage swing 1,4 Volt. The simulation results in phase noise performance at five offset frequency reference show that all point are fulfill requirements derived before. text
institution Institut Teknologi Bandung
building Institut Teknologi Bandung Library
continent Asia
country Indonesia
Indonesia
content_provider Institut Teknologi Bandung
collection Digital ITB
language Indonesia
description In this final project, a frequency synthesizer for WiMAX subscriber-station is presented. Based on a phase-locked loop, the synthesizer can provide various channel selection to cover 1,75 MHz channel bandwidth or its multiply. A programmable divider is proposed using traditional fractional-n or usually called pulse-swallow divider scheme.<p> <br /> <br /> <br /> <br /> <br /> Phase noise of a PLL synthesizer is a major one-chip solution design consideration. A phase noise requirement is firstly derived from spectral emission specification on the IEEE 802.16-2004 standard. Then the frequency synthesizer's components are designed to fulfill those requirements. The derived phase noise requirement was on five point references.<p> <br /> <br /> <br /> <br /> <br /> The frequency synthesizer consists of PFD, Charge-pump, Loop filter, VCO, and Divider circuit. The VCO is using negative-Gm oscillator topology. This oscillator does not need any extra circuitry to maintain its amplitude. The capacitance which is usually connected in parallel with the inductance to form the LC-tank is divided into 2 similar varactor. The control voltage to the varactor was single ended due to simplicity design on the charge-pump and loop filter.<p> <br /> <br /> <br /> <br /> <br /> The frequency synthesizer was simulated using RF transistor available in AMS 0.35 um technology kit. The VCO control voltage can be tuned between 1,2-5 Volt. The VCO output frequency at 3.5 volt control voltage is 2.338 GHz. The VCO output is a differential signal with voltage swing 1,4 Volt. The simulation results in phase noise performance at five offset frequency reference show that all point are fulfill requirements derived before.
format Final Project
author BASKORO (NIM 13204005), FARID
spellingShingle BASKORO (NIM 13204005), FARID
#TITLE_ALTERNATIVE#
author_facet BASKORO (NIM 13204005), FARID
author_sort BASKORO (NIM 13204005), FARID
title #TITLE_ALTERNATIVE#
title_short #TITLE_ALTERNATIVE#
title_full #TITLE_ALTERNATIVE#
title_fullStr #TITLE_ALTERNATIVE#
title_full_unstemmed #TITLE_ALTERNATIVE#
title_sort #title_alternative#
url https://digilib.itb.ac.id/gdl/view/10409
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