#TITLE_ALTERNATIVE#

• Main Author: HERI KURNIAWAN (NIM 13204093), IPUT
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/10680
• Institution: Institut Teknologi Bandung

RSA is one of the cryptography method used asimetric cryptography system. Asimetric cryptography is the encryption and decryption used 2 different keys. One of the application RSA is used in email encryption and file encryption that is PGP(Pretty Good Privacy), for e-commerce encryption system is SSL(Secure Socket Layer). RSA is made to solve the weakness of cryptography asimetric.<p> <br /> <br /> <br /> <br /> <br /> Compared with asimetric cryptography, encryption and decryption asimetric processing is relatively very slow and complexs, because it computes arithmatic exponentiation big number operation.<p> <br /> <br /> <br /> <br /> <br /> Algorithm which is choosed is Optimized radix-4 Montgomery because its algorithm has iteration number of modular multiply operation 1/2 n + 1. Compared with radix-2 Montgomery only has n iteration number of multiply operation. Optimization of radix-4 Montgomery is done by replacing full adder operation with 2 carry-save adder.<p> <br /> <br /> <br /> <br /> <br /> The designing is start by modelling RSA on Matlab and verilog language. Then making the RSA key generator program and designing the core of RSA with verilog language. Its model is used as reference to verifying core design.<p> <br /> <br /> <br /> <br /> <br /> The core is designed by implemented matlab or verilog model programs. Its algoritm based on optimazed radix-4 Montgomery and modular exponentiation Square and multiply. Verifying and Implementation in FPGA is done with Mentor Graphic Modelsim 6.0 and Altera Quartus 7.2 softwares also board FPGA Altera DE2 EP2C35F672C6 hardware. Implementation is done by connecting monitor with FPGA pass through VGA port and processing encryption and decryption image. Therefore in monitor will appear 3 images that are original image, encryption image and decryption image. Hardware verifying is done by comparing decryption image with original image in monitor. Synthesis result showing that clock speed is variatif depend on complexity of RSA. For size 32-bit the design is able to work at frequency 115 MHz (frequency maximum), while for size 512-bit the design is able to work at frequency 20 MHz (maximum frequency). The latency design is 227K for RSA 512-bit.