#TITLE_ALTERNATIVE#

• Main Author: (NIM 13203077), RUDY
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/11348
• Institution: Institut Teknologi Bandung

<p align="justify">Channel coding is a part used by many digital communication systems nowadays in order to enhance the ability of the code to fight the influence of channel noise. One of the most used channel coding methods for the purpose is the convolutional encoder in the transmission side and Viterbi decoder in the receiver side.<p align="justify"><p>The focus of this project is designing and implementing Viterbi decoder using VHDL (Very-High-Speed-IC Hardware Description Language). Selected design parameters are: constraint length K = 9, code rate = 1/2, and generator polynomial of [561 753]8.<p align="justify"><p>Viterbi decoder design is carried out by focusing on the usage of the so-called in-place scheduling technic in designing efficient path metric storage memory, so as the total area of the memory and its ahead interconnection with ACS (add-compare-select) unit can be reduced. Decoder is also designed with 5 bit quantization soft decision input from demodulator. Path metric normalization uses modular arithmatic technic to meet the criteria of uniformity and locality of the ACS.<p align="justify"><p>Design result with VHDL is then simulated with Modelsim 6.2 and Quartus II software. Simulation result is automatically compared with MATLAB simulation result on a test bench. Circuit is also synthesized with Synopsys and Quartus II on FPGA Altera Cyclone II EP2C35F672C6N board. The synthesized result using Synopsys gives the value of total area 7793865.2 um2 and delay of 6.01 ns. As the synthesized result using Altera Quartus II gives the usage of 6146 logic elements, 4509 registers, and 65536 of total memory bits for the decoder design. The circuit can run with maximum clock frequency of 105.92 MHz. <br />