#TITLE_ALTERNATIVE#

• Main Author: SALIM (NIM 13202143), SIGIT
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/11409
• Institution: Institut Teknologi Bandung

<p align="justify">Voice communication using power line as the transmission medium is a solution for high cost in providing new facilitation because its availability, but the characteristic of power line is not good for voice communication. In power line, the level of noise is high so it can disturb the communication. To overcome the problem, a modulation scheme which has good performance against noise is needed.<p align="justify"><p>DSSS is a technique which uses a large bandwidth to carry information signal. The main benefit that DSSS possessed is it has good performance in the presence of noise so it can accommodate the need for a modulation scheme at power line. DSSS uses PN code to spread the information signal to a wide bandwidth and RF signal for modulation. Receiver must be able to track the PN code and RF signal used.<p align="justify"><p>In this final project, a chip is designed for voice communication over power line. The steps of design consist of modeling the chip using VHDL syntax and simulation using ModelSim and Xilinx. The simulation using ModelSim shows that the chip produces a good result at tracking process of PN code. For tracking process of RF signal, the chip is able to track RF signal too, but the result isn't perfect yet because the phase offset between RF signal used by transmitter and receiver reach 1/4 period. This amount of phase offset decreases noise margin for 6.02 dB. Using Xilinx simulator, it's known that PNG_block is the biggest part of the design. Xilinx also shows the maximum frequency for design is 45.179 MHz and total logic gate used are 41,320 gates. <br />