#TITLE_ALTERNATIVE#

• Main Author: TRIYANTO (NIM 23205043); PEmbimbing : Ir. Eniman Yunus Syamsudin, M.Sc, Ph.D., DEDI
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/13366
• Institution: Institut Teknologi Bandung

Automatic controller used generally in industry are proportional controller (P), proportional integral controller (PI), proportional derivative controller (PD) and proportional integral derivative controller (PID). Each the controller optimum only when used for the case of certain. In this research, digital controller designed which its function can changed into every function from the automatic controller. Result of digital controller design has been implemented on Field Programmable Gate Array (FPGA).<p>Design process is started by designing modules of digital controller peripheral based on general equation of controller P, PI, PD and PID. Design peripheral which used is Verilog Hardware Description Language (Verilog HDL). Next step is simulation process in form of functional simulation and timing simulation using the Quartus II 6.0. Simulation process started with functional simulation for modules in system then continued with digital controller system simulation. Result from timing simulation indicate that the maximum frequency which can be used on digital controller is 4.73 MHz or on minimum period 211.6 ns.<p> Then, result of digital controller design is implemented on Altera UP2 Education Board or precisely on EPF10K70RC240-4 chip. Based on implementation task result, total of Logic Cells (LC) used is 1.424 / 3.744 (38 %). In-circuit Verification is process to test the digital controller implementation on FPGA. At verification process, frequency used on digital controller is 3.150 MHZ or with period 317.5 ns. While sampling frequency which can be used is 8 Hz (T = 0.125 s), 4 Hz (T = 0.25 s), and 2 Hz (T = 0.5 s). Verification is executed in each form of controller P, PI, PD and PID. Verification to each form of controller and different sampling time yield the maximum mean error level is 9.59 %. Results from verification process indicate that the output from digital controller that is control signal own the pattern matching with wanted pattern signal. This is indication that digital controller have functioned better. Result of examination also show the influence of sampling time, that is increase of sampling time used hence system tend to oscillation.