#TITLE_ALTERNATIVE#

• Main Author: Christanto (NIM : 13205194), Eric
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/13435
• Institution: Institut Teknologi Bandung

It is really hard right now to make a single core processor have higher clock frequency to increase its performance. Because of this reason, many chip processor producer try to develop multi-core technology. Multi-core is one chip processor with many cores inside it. This term <br /> <br /> <br /> <br /> <br /> should not be confused with multiprocessor. Multiprocessor means more than one processor that physically separated, but work together in a system computer. As the gap between CPU and main memory increased, system designer made a small fast storage device which called as cache to overcome this problem. Cache has access speed faster <br /> <br /> <br /> <br /> <br /> than memory, but still slower than CPU registers speed. The cache size is bigger than CPU register, but smaller than main memory capacity. The use of private cache in multi-core and multiprocessor will always face a problem with data consistency between caches. This problem is commonly known as cache coherence problem. The simplest solution to this problem is using invalidation based protocol with snooping. In this final task will be made a simulator to simulate the work and performance of the cache <br /> <br /> <br /> <br /> <br /> of dual core processor use MESI cache coherence protocol with private L1 cache for each core and shared L2 cache for all cores. Cache performance is judged by hit and misses percentage in read or writes from a sequence of memory address at cache. This simulator is built using C <br /> <br /> <br /> <br /> <br /> language program with MinGW compiler. The simulator will get 2 trace file in dinero format as its input. Program will read these 2 dinero trace file by turn.