ASYNCHRONOUS CACHE IMPLEMENTATION AND SIMULATION WITH VHDL

• Main Author: LUWIS (NIM: 13205019), ERWIN
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/13443
• Institution: Institut Teknologi Bandung

These days the development of computer technology began experiencing stagnation due to the problems such as clock skew and high power consumption. Various solutions have been developed to overcome this problems, one of them is <br /> <br /> <br /> <br /> <br /> asynchronous technology, which is a technology that does not use the clock, with this the clock skew can be avoided and this technology has relatively small power consumption compared with the synchronous system. However, behind all the advantages, the development of asynchronous system still has many obstacles such as design complexity as well as limited design tools for the development of asynchronous systems. This final year project is try to answer these obstacles by designing an asynchronous cache system with specification, a 4-way set associative cache, <br /> <br /> <br /> <br /> <br /> write-back and write-allocate write policy, and the least recently used replacement policy, and a simple asynchronous RAM for simulation purposes and simulate it <br /> <br /> <br /> <br /> <br /> by using the VHDL programming language and compiler Altera Quartus II, which is a synchronous system compiler which has been widely known. Simulation results obtained from the processing of this final task project indicate <br /> <br /> <br /> <br /> <br /> that an asynchronous system can be designed using VHDL language and simulated well with Altera Quartus II compiler. This result is expected to encourage the developers to develop asynchronous systems. Timing diagram, the netlist viewer and the compilation report viewer is used to analyze asynchronous cache created in this final year project.