PREPROCESSING AND SORTING MODULE ARCHITECTURE DESIGN AND IMPLEMENTATION FOR GRAPH BASED IMAGE SEGMENTATION
Growing technology makes processing faster dan able to perform realtime processing. Delivering an information from point to point will be very fast. Image processing become increasingly populer in the development of the digital world. Image sequence processing can be done in realtime with complex ha...
Saved in:
| Main Author: | |
|---|---|
| Format: | Final Project |
| Language: | Indonesia |
| Online Access: | https://digilib.itb.ac.id/gdl/view/14973 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Institut Teknologi Bandung |
| Language: | Indonesia |
| Summary: | Growing technology makes processing faster dan able to perform realtime processing. Delivering an information from point to point will be very fast. Image processing become increasingly populer in the development of the digital world. Image sequence processing can be done in realtime with complex hardware that was designed. Speed of sequences determined in units of frame per second. In this final project, the author developed and implemented the graph-based image segmentation. Image segmentation must be able to process the image with a speed of 60 fps with frame size of 320 * 240 pixels. Design of image segmentation is begun with selecting algorithm then made in C codes. Verilog code is used to implement RTL code in hardware. Functional verification is done by simulator software. Synthesis performed with Xilinx ISE software and Design Compiler® for a gate-level netlist. The result of final project is achieved speeds of 181 MHz if synthesized with ISE Xilinx®. Estimated area and timing obtained by Design Compiler® is 180,259 and 108 MHz (9.24 ns) with class.db library. By this achievement, the system need ASIC library that has speed of computing 122% faster than ASIC standard library. |
|---|