#TITLE_ALTERNATIVE#

• Main Author: HUTAMA SUSILO (NIM: 13206067); pembimbing :Trio Adiono, ST., MT., Ph.D, BRIAN
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/15190
• Institution: Institut Teknologi Bandung

As an high populated emerging country, Indonesia has millions of students who needs personal computers for educational and work practice needs. Indonesian personal computer penetration based on statistic in 2009 is only 6%, which is very small. So that, development of low cost personal computers is needed. In 2006, Sun Microsystem opened and released SPARC processor design. The design which is called OpenSPARC, has open source RTL (Register Transfer Level design) in Verilog HDL. This open source processor design could be used to solve Indonesian computer needs. Wishbone bus is and open source bus design which has detailed specification and well maintained by Open Cores Organization. The Wishbone Bus design also has many compatible open source IP Cores for peripherals. To simplify and fasten the development process, OpenSPARC reference design which use Wishbone bus is selected. In this final project, the OpenSPARC reference design is compared and selected to prepare the bus and peripherals design, then the functionality of the design is tested and verified. The timing and operation of OpenSPARC and Wishbone bus are extracted. After that, the interrupt mechanism is added and designed, then the bus is designed to connect GPIO, UART, PS/2, Timer and RAM peripherals. Due to the limitation of information and technical support, the bus and peripherals design still cannot communicate perfectly with the OpenSPARC core, but that limitation is solved by designing a Wishbone Bus Master which imitates OpenSPARC core input output operation based on the previous extraction. The result is an bus and peripherals design which complies with OpenSPARC input output and Wishbone Bus access method.