#TITLE_ALTERNATIVE#

• Main Author: AMI SOETHARYO (NIM: 132051630); Pembimbing : Ir. Achmad Fuad Mas’ud, M.Eng., NOVENA
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/16721
• Institution: Institut Teknologi Bandung

This final year project covers the design of Thumb instruction set handling for Tiny-ARM32 processor. All completed designs are modeled in VHDL (Very High Speed Integrated Circuit Hardware Design Language) for ease in synthesis and test of functionality. Tiny-ARM32 processor is a simplified implementation of a small section of the popular mobile-friendly ARM instructions, completed by Felis Dwiyasa. The core is also supported with a hierarchy of L1 and L2 cache along with a cache control system to store data. The design process of Thumb instruction set handling for the processor is carried out as a foundation to achieve higher instruction density for the processor. <br /> <br /> <br /> As a main component in Thumb instruction set handling, a decompressor is designed to translate the 16 bit Thumb instructions into 32 bit ARM instructions. A new instruction type, branch and exchange, is also added into the design to enable processor to operate dynamically between ARM or Thumb state. CPSR as flag storage to guide the processor is also altered to assist the use of Thumb bit. All enhancements designed are then integrated into the processor as a whole design. Synthesis report shows that Thumb-enabled Tiny-ARM32 core uses up to 3,158 Look-Up Tables, 1,197 registers, and 150,016 memory bits in target device FPGA EP2S15F484C3, of Stratix II family, from. Altera. Timing analysis report shows that maximum delay in the design is 19.339 ns, which enables the design to operate at a maximum frequency of 51.71 MHz. Verification is done via various test vectors and all results show that the design for Thumb instruction set handling for Tiny-ARM32 processor is fully functional.