DESIGN AND IMPLEMENTATION OF SMART CARD READER ON ZYNQ-7000 SYSTEM ON CHIP

• Main Author: CANDRA SWASTIKA - NIM: 23215339 , ADI
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/24990
• Institution: Institut Teknologi Bandung

<p align="justify">The growing use of smart cards that are increasingly massive make the need for smart card reader becomes higher. Nowadays, smart card reader is required not only to read data on smart cards. The trend of integration in the digital world makes smart card reader is expected to be able to be integrated with various features such as internet connectivity, LCD display, and be able to work as a standalone. <br /> <br /> <br /> One of the solutions to overcome the above problems is to design a smart card reader in the form of IP core, then implement it on System-on-Chip (SoC). Implementation of smart card reader in the form of IP core makes the smart card reader design becomes flexible, so the design can be integrated with various features mentioned above. In addition, it also makes smart card reader design to have a high reusability. Furthermore, SoC that basically integrates various components on a single chip can offer higher processing speed with a relatively low power consumption. <br /> <br /> <br /> In this research, smart card IP core is implemented on Zynq-7000 SoC using Zybo™ development board. There are two main parts in Zynq-7000 namely processing system and programmable logic. Smart card IP core is implemented on the programmable logic while input and output data processing are done on the processing system. IP Core design is done using Vivado Design Suite software, while the design on the processing system is designed using Xilinx SDK. In the end, both designs are integrated through AXI interconnect. The IP core itself has two main parts, namely receiver and transmitter. In the receiver, there are data processing blocks, such as: clock divider, start bit detection, data sampling, parity, data stacking, data parsing, and error signaling. In the transmitter, there are several blocks, such as: data concatenation, data parsing, and parity block. <br /> <br /> <br /> The smart card that is used in this research is contact smart card with ISO/IEC 7816 standard, so that IP core design reffers to the same standard. The results of the implementation will be analyzed and compared to other smart card reader which in this case is ACR38U-I1. From the results analysis, it is known that the speed performance of smart card designed in this study is better than similar smart card reader. <p align="justify">