DEVELOPMENT OF IoT AUTHENTICATION MECHANISMS WITH PHYSICALLY UNCLONABLE FUNCTION (PUF) AS KEY TO DATA SHIPPING ON MICRO GRID APPLICATION

• Main Author: PRAMUDITA - NIM : 23215111 , RESA
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/30334
• Institution: Institut Teknologi Bandung

<p align="justify">Information security is a crucial problem in a microgrid system. In this research work, an authentication scheme and the implementation of Physically Unclonable Function (PUF) as a key generator for the authentication system are developed. For authentication mechanisms, the system has authentication capabilities and access control by assigning IDs to each gateway. The main issues investigated for PUF in this works covers both the uniqueness and reliability aspects. The system developed here uses AES algorithm for encryption, and SHA-256 for the hash function. The type of PUF used in this research is delay PUF which utilizes Ring Oscilator circuits (ROPUF). This authentication scheme is implemented using Raspberry Pi 3 platform with Python programming language whereas ROPUF is implemented in an FPGA module. The functionality tests of parts of the module which include of the hash function, encryption algorithm, and data delivery testing using real data show that the system is functioning properly. For testing the occurrence probability of a value 1 or P(bi=1) for each bit, two FPGA boards, designated as FPGA 1 and FPGA 2 were used. In FPGA 1, the largest value of P(bi=1) is found to be at the first bit and the smallest value of P(bi=1) is at the fourth bit. For FPGA 2, the largest value of P(bi=1) is at the 13th bit, and the smallest value of P(bi=1) is at the 12th bit. For the average stability value at any position expressed by the Si parameter, the largest Si value on FPGA 1 is at the 4th bit position and the smallest is at the 11th bit. For FPGA 2, the largest Si value is on the 12th bit while the smallest one is at position 11. In this work, the Hamming distance (HD) of the ROPUF output of both FPGA 1 and 2 are analyzed. For the two FPGA’s, the Intra HD results are found to be unsastisfactory because there are still many changes in bit value (bit-flip) are within 1 – 2 bits. On the other hand, the Inter HD values obtained appear to be adequate with the average bit-flip in the range of 3-4 bits. This can be caused by the influence of random environmental conditions, for example due to the fluctuations of ambient temperature.<p align="justify">