DESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION
Avionics Digital Video Bus (ADVB) is a high-bandwidth with critical data avionics video transmission system. ADVB does not have an error correction implemented, but it uses 8B/10B coding to maintain DC-balance. In this thesis, a design of an error correction system is implemented to a video transmis...
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id-itb.:370742019-03-18T14:30:21ZDESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION Prihatiningrum, Novi Indonesia Theses error correction, two-dimensional parity, 8B/10B coding. INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/37074 Avionics Digital Video Bus (ADVB) is a high-bandwidth with critical data avionics video transmission system. ADVB does not have an error correction implemented, but it uses 8B/10B coding to maintain DC-balance. In this thesis, a design of an error correction system is implemented to a video transmission system with available 8B/10B coding. The designed error correction uses two-dimensional parity with its horizontal parity from 8B/10B coding error detection capability. Simulation is done for various frame size and the result shows that a lower bit error rate and frame error rate is achieved from a larger frame size. The use of this error correction system affects significantly at SNR value more than 7 dB. This error correction system is implemented in FPGA and the result shows a higher resource usage and latency for larger frame size. text |
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Institut Teknologi Bandung |
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Indonesia Indonesia |
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Institut Teknologi Bandung |
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Indonesia |
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Avionics Digital Video Bus (ADVB) is a high-bandwidth with critical data avionics video transmission system. ADVB does not have an error correction implemented, but it uses 8B/10B coding to maintain DC-balance. In this thesis, a design of an error correction system is implemented to a video transmission system with available 8B/10B coding. The designed error correction uses two-dimensional parity with its horizontal parity from 8B/10B coding error detection capability. Simulation is done for various frame size and the result shows that a lower bit error rate and frame error rate is achieved from a larger frame size. The use of this error correction system affects significantly at SNR value more than 7 dB. This error correction system is implemented in FPGA and the result shows a higher resource usage and latency for larger frame size. |
| format |
Theses |
| author |
Prihatiningrum, Novi |
| spellingShingle |
Prihatiningrum, Novi DESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION |
| author_facet |
Prihatiningrum, Novi |
| author_sort |
Prihatiningrum, Novi |
| title |
DESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION |
| title_short |
DESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION |
| title_full |
DESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION |
| title_fullStr |
DESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION |
| title_full_unstemmed |
DESIGN AND IMPLEMENTATION OF 8B/10B CODING WITH 2D PARITY BASED ERROR CORRECTION |
| title_sort |
design and implementation of 8b/10b coding with 2d parity based error correction |
| url |
https://digilib.itb.ac.id/gdl/view/37074 |
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1822924809239003136 |