ASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG
In this thesis a demodulator circuit block is designed as part of passive UHF RFID tag. The demodulator block function is to extract the modulated information signal at the RF signal input to the digital signal output. The circuit specifications of this design are derived from EPC Class-1 Generat...
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id-itb.:393212019-06-25T14:53:23ZASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG Hidayana Hendrayana, Yusuf Indonesia Theses RFID, demodulator, UHF, envelope detector, comparator. INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/39321 In this thesis a demodulator circuit block is designed as part of passive UHF RFID tag. The demodulator block function is to extract the modulated information signal at the RF signal input to the digital signal output. The circuit specifications of this design are derived from EPC Class-1 Generation-2 standards which complies to ISO 18000-6C. All circuits design in this thesis are done in 130 nm CMOS technology. The demodulator is designed with an envelope detector and comparator circuit. The demodulator design results are then simulated with the corner method for the ASK signal’s amplitude and bit rates. Simulation shows that the designed demodulator has worked as intented for typical ASK-PIE signals input Vpeak of 250 mV with a tolerance of ± 20%. Demodulator works in 6.25 ?s Tari for various bit rates from 80 kbps to 160 kbps as required by the standard. According to the temperature test, the demodulator is able to work in the temperature of -25 oC to 40 oC. Layout design also has been made according to the schematic design and has been verified with DRC, LVS, and ERC. text |
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description |
In this thesis a demodulator circuit block is designed as part of passive UHF
RFID tag. The demodulator block function is to extract the modulated
information signal at the RF signal input to the digital signal output. The circuit
specifications of this design are derived from EPC Class-1 Generation-2
standards which complies to ISO 18000-6C. All circuits design in this thesis are
done in 130 nm CMOS technology. The demodulator is designed with an envelope
detector and comparator circuit. The demodulator design results are then
simulated with the corner method for the ASK signal’s amplitude and bit rates.
Simulation shows that the designed demodulator has worked as intented for
typical ASK-PIE signals input Vpeak of 250 mV with a tolerance of ± 20%.
Demodulator works in 6.25 ?s Tari for various bit rates from 80 kbps to 160 kbps
as required by the standard. According to the temperature test, the demodulator is
able to work in the temperature of -25 oC to 40 oC. Layout design also has been
made according to the schematic design and has been verified with DRC, LVS,
and ERC. |
format |
Theses |
author |
Hidayana Hendrayana, Yusuf |
spellingShingle |
Hidayana Hendrayana, Yusuf ASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG |
author_facet |
Hidayana Hendrayana, Yusuf |
author_sort |
Hidayana Hendrayana, Yusuf |
title |
ASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG |
title_short |
ASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG |
title_full |
ASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG |
title_fullStr |
ASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG |
title_full_unstemmed |
ASK DEMODULATOR DESIGN FOR PASSIVE UHF RFID TAG |
title_sort |
ask demodulator design for passive uhf rfid tag |
url |
https://digilib.itb.ac.id/gdl/view/39321 |
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1822925257868050432 |