PERANCANGAN DAN IMPLEMENTASI SISTEM KOMPRESI/DEKOMPRESI SPEECH PADA LOGIC CELL ARRAY DENGAN TRANSFORMASI DCT
<b>Abstract :</b><p align=\"justify\"> <br /> This thesis presents the design and implementation of lossy compression method for speech signal. The scheme of this method consists of preprocessing, quantization and coding. Discrete Cosine Transform (DCT) is used for...
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| Format: | Theses |
| Language: | Indonesia |
| Subjects: | |
| Online Access: | https://digilib.itb.ac.id/gdl/view/4851 |
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| Institution: | Institut Teknologi Bandung |
| Language: | Indonesia |
| Summary: | <b>Abstract :</b><p align=\"justify\"> <br />
This thesis presents the design and implementation of lossy compression method for speech signal. The scheme of this method consists of preprocessing, quantization and coding. Discrete Cosine Transform (DCT) is used for the preprocessing of the scheme. Runlength coding algorithm is used for the coding. For the efficiency, the output of quantization is rearranged prior to the coding.<p align=\"justify\"> <br />
The design of the compression and decompression modules are written in VHDL. After compiling, synthesizing and simulation, it is then implemented and verified on LCA XC4010EPC84-4 of Xilinx Inc. The result of static timing analysis is that the maximum clock frequency for the compression and decompression chip is 2.5 MHz and 3.8 MHz, respectively. The propagation delay for each of them is 45.1 ns and 42.6 ns, respectively. The verification used clock frequency of 16 KHz.<p align=\"justify\"> <br />
The verification of compression chip for 100 frames speech signal shows that the average compression factor is 16:1. Meanwhile, for the compression and decompression system, the Signal-to-Noise Ratio (SNR) is 23 dB, at the ratio, the speech is still recognizable. |
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