OVERLAY PROCESSING SYSTEM (PS) TO PROGRAMMABLE LOGIC (PL) AND RVFPGA SYSTEM FOR COMPUTER ARCHITECTURE EDUCATION

• Main Author: Oktavia Devi, Chyndi
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/66470
• Institution: Institut Teknologi Bandung

Computer architecture education is one of crucial topic for students studying computer science or engineering. In studying computer architecture itself there are various types of processors that can be studied such as MIPS, PIC, AVR, etc. It is a challenge for educators to decide which architecture should be utilized to teach computer architecture because of the variation of processors available (Jamieson et al, 2019). The several well-known computer architecture learning books published worldwide that use various architectures serve as evidence of the differences in how this architecture is used. One of the many types of processors that are available has the potential to be employed because it is open source and has been widely adopted by numerous colleges and significant global corporations. It's initiate the emergence of a problem regarding the need for a framework or tool to support RISC-V learning or research activities. To solve this problem, several stages are carried out in order to obtain the best solution. Beginning with an analysis of RISC-V????s economics, manufacturability, sustainability, education, and social aspects. Following this analysis, a list of requirements for a solution is developed, along with descriptions of a number of potential solutions. Some proposed solutions will analyzed and the best solution will be used for RISC-V????s visuali????ation and implementation. The next stage after coming up with a solution is to decide what requirements need to be met for the manufactured product and then create a number of system designs based on it. After the best system design is selected, implementation and testing of the system that has been created is carried out. The product to solve the problem of RISC-V needs for educational support is divided into three parts, namely a simulator, PS to PL overlay, control unit and RISC-V implementation on PYNQ-Z1. Just concentrate on the PS to PL overlay for this last project. This PS and PL overlay was created for one of the chapters in the RISC-V-based computer architecture learning module using the PYNQ-Z1 FPGA board. This PS to PL overlay can meet some part of the overall product specifications, there are RTL can be implemented on an FPGA, use FPGA with additional processors, and one part of a learning module. A simulation of the RVfpga system using the SweRV EH1 core, verilator, and whisper is also included. The SweRV EH1 is a 32-bit processor with 9-stage pipelined stages: fetch1, fetch2, align, decode, EX1/M1, EX2/M2, EX3/M3, commit, and writeback. The instructions for each step on the SweRV EH1 and the various simulation methods using the verilator and whisper are visible from the simulation results. The RVfpga system has input/output system with seven peripherals that can be used, but the implementation in this final project is only carried out for 2 peripherals, namely using GPIO to control switches and leds and using 8-digit 7-segment to display numbers.