PENGEMBANGAN AKSELERATOR PERANGKAT KERAS BERBASIS RISC-V UNTUK REINFORCEMENT LEARNING

• Main Author: Sulthan Mazaya, Muhammad
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/81535
• Institution: Institut Teknologi Bandung

Reinforcement Learning (RL) is one of the popular frameworks for developing autonomous agents. RL sewes as an alternative modeling solution for problems in systems that are too complex to be mathematically or algorithmically modeled. As a result, RL is widely emplo yed in domains such as robotics and autonomous driver agents. However, despite being a suitable alternative for many problems, RL is ofien challenging to use due to hardware resource limitations. This is primarily because RL typically demands significant hardware resources. This can be a hindrance when de¿iloying RL models on computers with limited resources, such as Internet of Things (IoT) devices or edge computing y7/aJorms. Therefore, in this research, a akselerator peranpkat keras design is proposed to reduce the computational power required for RL algorithm computation. This akselerator perangkat keras design will be imfilemented on a Field Programmable Gate Array with an RISC-V, an O yen instruction set architecture, architecture in the form of a co-F rocessor The results achieved in this final project consist of hardware and software configurations, along with the design of the software and hardware that will be implemented. Keywords: reinforcement learning, co-processor, field programmable gate array, RISC-V