#TITLE_ALTERNATIVE#

• Main Author: Syafiq Irsyadi (NIM 132 03 025) , Muh
• Format: Final Project
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/8738
• Institution: Institut Teknologi Bandung

Abstract: <br /> <br /> <br /> <br /> <br /> DVB-T is a standard used by DVB European Consortium Standard for digital terre-strial television broadcasting. DVB-T use a modulation technique called OFDM for their transmission system. This modulation uses IFFT algorithm and FFT algorithm to transform signals from frequency domain to time domain and from time domain to frequency domain respectively. <br /> <br /> <br /> <br /> <br /> The 2k FFT-IFFT Core supports FFT and IFFT computation for 2048-point DFT. The Core is designed using Radix-4/8 algorithm. This algorithm has the lowest arithmetic computations compared to lower radix algorithm. In addition, the Core design is based on Pipeline Single Path Delay Feedback Architecture. Pipeline archi-tecture has high throughput characteristic and Single Path Delay Feedback is the most memory efficient architecture compared to other pipeline architecture. <br /> <br /> <br /> <br /> <br /> The design process is started by formulating the mathematical description of the al-gorithm. The next steps are Matlab modeling, datapath design, and control unit de-sign. Datapath is designed using fixed-point format with variable datapath approach. VHDL is used to implement the design into hardware description language. The de-sign is synthesized using Xilinx ISE 9.1i and implemented on Virtex-4 XC4VSX35-10F668 FPGA. <br /> <br /> <br /> <br /> <br /> Synthesis result shows that the design is able to work at 61 MHz (maximum frequen-cy). FPGA system prototype shows that at the working frequency (40 MHz), the Core throughput is 39.7 M symbol/s with continuous input. <br />