MOTION COMPENSATOR DESIGN AND INTEGRATION DECODER H.264

• Main Author: SUKRA (NIM 23206010), ZENER
• Format: Theses
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/9741
• Institution: Institut Teknologi Bandung

Digital video transmission technology has been commonly used these days. In this thesis, the author designs Motion Compensator and the Integration of Decoder System based on MPEG4 H.264/AVC. Decoder has a function to reconstruct image from the compressed original image. Three main components of MPEG4 H.264/AVC decoder are Inverse Block Transform, Deblocking Filter, and Motion Compensator. Motion Compensator produces prediction frame from one or two references that have been chosen from some reference pictures. Inverse Block Transform does decompression process to the input that has been accepted from NAL (Network Abstraction Layer) and entropi decode. Deblocking Filter reduces distortion in inter block border in a macro block. Motion Compensator is designed to support the operation with half pixel and quarter pixel resolution. Integration process requires addressing module and efficient buffer design. Addressing module eases data replacement and data's function and setting identification in a frame. Buffer adjusts data flow inter Decoder modules. The design is done in RTL using HDL Verilog language. The testing is done by comparing file which is the design result with reference data that has been obtained from reference software H.264 jm11.0 from standard ITU-T. Then, it is continued by implementation process using Synopsys Design Analyzer. Beside for the implementation in standard cell, this process also shows that the design result can be synthesized in logic level. The result obtained displays pixel difference between simulation data and reference data is approximately 5%. This difference is still tolerated because it can be considered as lossy compression and does not influence picture quality seen from the sight aspect. Time needed for decoding 30 frames is 4.936.140 clk. It shows that the system can run real-time with minimum speed 50MHz. <br /> <br />