Implementasi pada FPGA atas SOVA Untuk Pengawasandian Turbo

• Main Authors: , DARYUS CHANDRA, , Ir. Budi Setiyanto, M.T.
• Format: Theses and Dissertations NonPeerReviewed
• Published: [Yogyakarta] : Universitas Gadjah Mada 2013
• Subjects: ETD
• Online Access: https://repository.ugm.ac.id/125104/; http://etd.ugm.ac.id/index.php?mod=penelitian_detail&sub=PenelitianDetail&act=view&typ=html&buku_id=65269

Turbo code is one the channel code schemes that gives the best error correcting capability nowadays. Because of its capability, turbo code is selected as the standard for fourth generation telecommunication technology (4G) such as WiMAX and LTE. There are two kinds of algorithm that widely used for decoding the turbo codes, those are Soft-Output Viterbi Algorithm (SO VA) dan Maximum A Posteriori Algorithm (MAP). MAP Algorithm gives a better result on error correcting capability but the consequence it has higher complexity algorithm, in contrary with SO VA. This paper presented a design for decoding turbo codes using SOVA with Very high speed integrated circuit Hardware Description Language (VHDL) as the modeling program and the design is implemented on the FPGA. Implementation result shows that SOVA occupies 159 slices or 3% of the available slices in Xilinx Spartan-3E, 105 flip flop (1%), 278 L UT (2%), and 141 IOB (60%) with maximum frequency clock is 43,384 MHz. SOVA decoder is able to correct up to six non-bursty error symbols from 16 received symbols but SOVA fails to perform its error-correcting capability for three consecutive error symbols. SOVA decoder can be implemented for turbo decoding by combining SOVA decoder with interleaver and deinterleaver.