IMPLEMENTASI PROGRAMMABLE DAC PADA FPGA XILINX SPARTAN-6 BERBASIS VHDL PROGRAMMABLE DAC IMPLEMENTATION ON XILINX FPGA SPARTAN-6 BASED ON VHDL

Development of digital design is on rapid progress. This makes it possible to implement a digital system design with many variations of base system. FPGA is a base system that can be used with advantage on speed processing because the design is implemented on hardware level. This current era have be...

Full description

Saved in:
Bibliographic Details
Main Authors: , AHMAD HANEEF ZUHDY, , Prof. Dr. Jazi Eko Istiyanto, M.Sc.
Format: Theses and Dissertations NonPeerReviewed
Published: [Yogyakarta] : Universitas Gadjah Mada 2013
Subjects:
ETD
Online Access:https://repository.ugm.ac.id/125327/
http://etd.ugm.ac.id/index.php?mod=penelitian_detail&sub=PenelitianDetail&act=view&typ=html&buku_id=65494
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Universitas Gadjah Mada
Description
Summary:Development of digital design is on rapid progress. This makes it possible to implement a digital system design with many variations of base system. FPGA is a base system that can be used with advantage on speed processing because the design is implemented on hardware level. This current era have been digitialization, where the analogue value have been converted to digital form. Therefore function of digital-to-analogue conversion (DAC) became one of commonly function used. This research implement DAC function into FPGA and can be programed by users, this system called programmable DAC. Programmable DAC was implemented on FPGA Spartan-6 LX45 embedded in Atlys Development Board. This implementation using VHDL to design. Programmable DAC was designed to reconstruct the signal using 2 method ie PWM and delta-sigma. This research uses MATLAB to calculate signal value. Then the data sent using USB-UART on Atlys development board. The signal value was processed by programmable DAC that been programmed on the FPGA. For smoothing the output using low pass filter with passive RC components. Then the Signal was generated through an oscilloscope. The reconstructed signal had same shape and frequency. Implementation uses 1% of the FPGA resources, precisely 75 LUTs and 65 Slices Register.