IMPLEMENTASI PADA FPGA ATAS ESTIMATOR HALUS DAN INTERPOLATOR DENGAN PENGALI BERBASIS UNTAI SEKUENSIAL UNTUK ESTIMASI KANAL OFDM

• Main Authors: , NOVIA WULANDARI, , Ir. Budi Setiyanto, MT.
• Format: Theses and Dissertations NonPeerReviewed
• Published: [Yogyakarta] : Universitas Gadjah Mada 2013
• Subjects: ETD
• Online Access: https://repository.ugm.ac.id/126570/; http://etd.ugm.ac.id/index.php?mod=penelitian_detail&sub=PenelitianDetail&act=view&typ=html&buku_id=66797
• Institution: Universitas Gadjah Mada

Orthogonal Frequency Division Multiplexing (OFDM) is a parallel data transmission scheme which is able to provide bandwidth eficiency and high bit rate. The existence of multipath fading in wireless communication cause ISI (Inter Simbol Interference) that implies the needs of smooth estimator and interpolator in OFDM receiver. Channel estimator with pilot simbol helps OFDM system to estimate channel characteristic. Sending a lot of pilot symbol will decrease the throughput. Limitation of pilot�s usage can be done by sending pilot symbol in certain subchannel, while subchannel that do not have pilot symbol will be estimated using interpolator. FPGA (Field Programmable Gate Array) is one of programmable device for digital system. FPGA is one of the devices that can be used to implement the smooth estimator and interpolator for channel equalizer. HDL (Hardware Description Language) is a language that is used to programing FPGA. The most popular HDL is VHDL (Very high speed integrated circuit Hardware Description Language). As a result, the implementation of cascaded smooth estimator and interpolator is able to show true performance and the output is agree with the result of Microsoft Excel. In terms of capacity, smooth estimator and interpolator design needs 2,276 slices and the maximum clock is 177,999 MHz.