DESAIN DAN ANALISIS FAULT TOLERANCE BERBASIS FPGA PADA ON-BOARD COMPUTER SATELIT MIKRO

• Main Authors: , haryono, , Prof. Jazi Eko Istiyanto, Ph.D
• 格式: Theses and Dissertations NonPeerReviewed
• 出版: [Yogyakarta] : Universitas Gadjah Mada 2014
• 主題: ETD
• 在線閱讀: https://repository.ugm.ac.id/134080/; http://etd.ugm.ac.id/index.php?mod=penelitian_detail&sub=PenelitianDetail&act=view&typ=html&buku_id=75064
• 機構: Universitas Gadjah Mada

Field Programmable Gate Array (FPGA) is susceptible to hazard radiation that leads to an error state, therefore fault tolerance is required. Most of fault tolerances today are only using one mode, mean the fault tolerance which isapplied will run all of the time without any changing its configuration. It is neglect about the condition, when the hazard radiation will occur more frequent or not. As researches have shown in the orbit, hazard radiation happends in South Atlantic Anomaly (SAA) frequently. Creates a new method by considering the radiation level will have a chance to have a fault tolerance which is more efficient. The new method is by designing a fault tolerance using dual mode. Implementing dual mode aims to create more efficient fault tolerance in using resources. When radiation happen frequently more robust fault tolerance is applied, ifnot frequent simple fault tolerance is used. A robust fault tolerance will use more resources and simple fault tolerance will use less resources. Switching between robust to simple fault tolerance or vice versa is done using Dynamic Partial Reconfiguration (DPR) technique therefore not distrubing to the system which is running. Dynamic Partial Reconfiguration (DPR) is a way to change the memory data in FPGA, it aims to change the configuration of FPGA without disturbing the operation which is running. By implementing above design showed that the system is more efficient. Consumming more resources happens only when the satellite in the critical area.