A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL

• Main Authors: Choi, Kyung-Sik, Kim, Keun-Mok, Utomo, Dzuhri Radityo, Lee, In-Young, Lee, Sang-Gug
• Format: Article PeerReviewed
• Language: English
• Published: IEEE 2022
• Subjects: Electrical and Electronic Engineering
• Online Access: https://repository.ugm.ac.id/278607/1/Utomo_TK.pdf; https://repository.ugm.ac.id/278607/; https://www.ieee.org/publications/rights/index.html; https://doi.org/10.1109/JSSC.2022.3159656
• Institution: Universitas Gadjah Mada

A fully integrated 490-GHz receiver (RX) adopting a dual-locking receiver-based FLL (DL-RBFLL) is presented. The proposed RBFLL structure saves the power consumption by reusing the existing blocks in RX instead of the power-hungry blocks such as dividers and buffers operating at sub-THz. Contrary to the single-loop implementation, the dual-loop RBFLL, which consists of the coarse and fine locking loops, extends the locking range by six times with negligible additional power dissipation. In the RF front-end (FE), the proposed 2nd-order sub-harmonic mixer (SHM) enhances interport isolation and suppresses the undesired LO leakage using a simple passive network. In the IF path, a 2-stage low-noise amplifier (LNA) followed by a 10-stage programmable gain amplifier provides a controllable gain of 0–80 dB with 4-dB step. An N-path filter, which serves as a high-Q bandpass noise filter, improves SNR in the IF path and thus RX sensitivity. Implemented in a 65-nm CMOS, the 490-GHz RX achieves the measured noise figure of 51.1 dB and noise equivalent power (NEP) of 0.85 pW/Hz0.5 for the noise bandwidth of 17 MHz. The estimated sensitivity of the proposed RX is −92.9 dBm for a 1 kHz noise bandwidth, which dissipates 31.8 mW from a 1.2-V supply.