Performance characterization of schottky tunneling Graphene Field Effect Transistor at 60 nm gate length
A planar Graphene Field-Effect Transistor GFET performance with 60 nm gate length was evaluated in discovering new material to meet the relentless demand for higher performance-power saving features. The ATHENA and ATLAS modules of SILVACO TCAD simulation tool was employed to virtually design and as...
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Main Authors: | , , , |
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Format: | Article |
Language: | English |
Published: |
Penerbit Universiti Kebangsaan Malaysia
2017
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Online Access: | http://journalarticle.ukm.my/11126/1/11%20Noor%20Faizah.pdf http://journalarticle.ukm.my/11126/ http://www.ukm.my/jsm/malay_journals/jilid46bil7_2017/KandunganJilid46Bil7_2017.html |
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Institution: | Universiti Kebangsaan Malaysia |
Language: | English |
Summary: | A planar Graphene Field-Effect Transistor GFET performance with 60 nm gate length was evaluated in discovering new material to meet the relentless demand for higher performance-power saving features. The ATHENA and ATLAS modules of SILVACO TCAD simulation tool was employed to virtually design and assess the electrical performance of GFET. The developed model was benchmarked with the established results obtained from the DESSIS simulator model by using the same graphene channel’s parameters and simulated at fixed threshold voltage of 0.4V. The GFET was also analyzed and ranked its performance for four different gate oxides which includes HfO2, Al2O3, TiO2, and Ta2O5. Compared to the benchmarked device, our GFET shows a competitive performance although it possesses a lower drive current (ION). However, the leakage current (IOFF), subthreshold swing (SS) and the device’s switching capability (ION/IOFF) are more superior than those of the benchmarked device, with an improvement of 99%, 48.3% and 99.36%, respectively. The with different gate dielectrics were also proven to possess a lower IOFF, competitive ION, smaller SS and better switching capability compared to the established DESSISS model. The graphene parameters in this experiment can be utilized for further optimization of GFET with smaller gate lengths. |
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