DESIGN-FOR-TESTABILITY (DFT) TECHNIQUE FOR OPEN FAULTS IN CMOS LATCH/FLIP-FLOP
In this report, CMOS 0-latch with and without open faults are designed. Schematics and layout are simulated using Cadence Spectre. The process parameter used in design is Technology AMJ06. The results obtained from the simulation are observed for both cases (with open and without open fault). It...
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| Main Author: | |
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| Format: | Final Year Project |
| Language: | English |
| Published: |
Universiti Teknologi Petronas
2008
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| Online Access: | http://utpedia.utp.edu.my/7139/1/2008%20-%20Design-for-test%20ability%20%28DFT%29%20technique%20for%20open%20faults%20in%20cmos%20latchflip-flop.pdf http://utpedia.utp.edu.my/7139/ |
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| Institution: | Universiti Teknologi Petronas |
| Language: | English |
| Summary: | In this report, CMOS 0-latch with and without open faults are designed.
Schematics and layout are simulated using Cadence Spectre. The process parameter
used in design is Technology AMJ06. The results obtained from the simulation are
observed for both cases (with open and without open fault). It is proven that there are
certain open locations in CMOS 0-latch could not be detected instantly. This is where
the purpose of designing the OFT comes in. OFT circuitry is added to the 0-Jatch to
create voltage competition in the circuit. With OFT circuitry implemented in the 0-
latch, the open fault can be detected easily. From observation, the output at the
memory state is flipped during testing. The layout for 0-latch with added OFT
circuitry is also included. |
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