A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design

In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We wi...

Full description

Saved in:
Bibliographic Details
Main Authors: Azman, Amelia Wong, Bigdeli, Abbas, Mohd-Mustafah, Yasir, Biglari-Abhari, Morteza, Lovell, Brian
Format: Conference or Workshop Item
Language:English
Published: 2010
Subjects:
Online Access:http://irep.iium.edu.my/102/1/ASAP.pdf
http://irep.iium.edu.my/102/
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5540784&isnumber=5540749
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Universiti Islam Antarabangsa Malaysia
Language: English