Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set

• Main Authors: Olanrewaju, Rashidah Funke, Fajingbesi, Fawwaz Eniola, Junaid, S. B., Alahudin, Ridzwan, Anwar, Farhat, pampori, Bisma Rasol
• Format: Article
• Language: English
• Published: Indian Society of Education and Environment 2017
• Subjects: TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices
• Online Access: http://irep.iium.edu.my/56118/1/Design%20of%20Pipeline%20published.pdf; http://irep.iium.edu.my/56118/; http://www.indjst.org/index.php/indjst/article/view/110622/77994
• Institution: Universiti Islam Antarabangsa Malaysia

In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle) CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined computer architecture, unprecedented improvement in size and...