A study on performance evaluation of conventional cache replacement algorithms: A review

• Main Authors: Olanrewaju, Rashidah Funke, Baba, Asifa Mehraj, Khan, Burhan Ul Islam, Yaacob, Mashkuri, Azman, Amelia Wong, Mir, Mohammad Shuaib
• Format: Conference or Workshop Item
• Language: English
• Published: IEEE 2017
• Subjects: TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices; TK7885 Computer engineering
• Online Access: http://irep.iium.edu.my/56847/7/56847.pdf; http://irep.iium.edu.my/56847/; http://ieeexplore.ieee.org/document/7913185/
• Institution: Universiti Islam Antarabangsa Malaysia

Cache Replacement Policies play a significant and contributory role in the context of determining the effectiveness of cache memory cells. It has also become one of the major key features for efficient memory management from the technological aspect. Hence, owing to the existing critical computing systems, it has become too essential to attain faster processing of executable instructions under any adverse situations. In the current scenario, the state of art processors such as Intel multi-core processors for application specific integrated circuits, usually employ various cache replacement policies such as Least Recently Used (LRU) and Pseudo LRU (PLRU), Round Robin, etc. However, fewer amounts of existing research works are found till date to utter about explicit performance issues associated with the conventional cache replacement algorithms. Therefore, the proposed study intended to carry out a performance evaluation to explore the design space of conventional cache replacement policies under SPEC CPU2000 benchmark suite. It initiates and configures the experimental Simple Scalar toolbox prototype on a wide range of cache sizes. The experimental outcomes obtained from the benchmark suite show that PLRU outperforms the conventional LRU concerning computational complexity and a variety of cache blocks organization.