Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari

In Semiconductor world, the design and fabrication of Integrated Circuit (IC) associated with development time, operating speed and power requirements. The goodness of each design must be evaluated before it is chosen, especially on speed of the circuits where it represent the time taken to execute...

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Main Author: Johari, Muhammad Aiman
Format: Thesis
Language:English
Published: 2015
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Online Access:http://ir.uitm.edu.my/id/eprint/21626/1/TM_MUHAMMAD%20AIMAN%20JOHARI%20EE%2015_5.pdf
http://ir.uitm.edu.my/id/eprint/21626/
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Institution: Universiti Teknologi Mara
Language: English
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spelling my.uitm.ir.216262018-09-26T03:19:57Z http://ir.uitm.edu.my/id/eprint/21626/ Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari Johari, Muhammad Aiman Microelectronics In Semiconductor world, the design and fabrication of Integrated Circuit (IC) associated with development time, operating speed and power requirements. The goodness of each design must be evaluated before it is chosen, especially on speed of the circuits where it represent the time taken to execute a specific function or most commonly known as delay. Conventional methods use repetitive manual testing guided by Logical Effort (LE). LE provides an easy way to compare and select circuit topologies, choose the best number of stages for path and estimate path delay. The proposal of Particle Swarm Optimization (PSO) with constriction factor (PSO-CF) and mutative variants (PSO-M) presented in this thesis attempts to create an automated process of transistor sizing optimization. The method attempts to get the target circuit delay on tested circuit's critical path based on LE calculation that accepts generated transistor size by both PSO variants as inputs to fitness function. The optimization of the transistor size will stop if maximum iteration reached of different between PSO's found delay and objective delay is very small (near or similar to c0'). Various parameters, such as swarm size and iterations were tested under different initial positions to verify PSO's performance on a adder circuits namely modified half-adder (M-HA), modified full-adder (M-FA) and modified ripple-carry adder (MRCA). The experiments reported in this thesis showed that both PSO variants were efficient to automatically find the optimum transistor size with solution range of [1(T2,1(T15] for PSO-CF and [10°, 1(T16] for PSO-M. 2015 Thesis NonPeerReviewed text en http://ir.uitm.edu.my/id/eprint/21626/1/TM_MUHAMMAD%20AIMAN%20JOHARI%20EE%2015_5.pdf Johari, Muhammad Aiman (2015) Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari. Masters thesis, Universiti Teknologi MARA.
institution Universiti Teknologi Mara
building Tun Abdul Razak Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Mara
content_source UiTM Institutional Repository
url_provider http://ir.uitm.edu.my/
language English
topic Microelectronics
spellingShingle Microelectronics
Johari, Muhammad Aiman
Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari
description In Semiconductor world, the design and fabrication of Integrated Circuit (IC) associated with development time, operating speed and power requirements. The goodness of each design must be evaluated before it is chosen, especially on speed of the circuits where it represent the time taken to execute a specific function or most commonly known as delay. Conventional methods use repetitive manual testing guided by Logical Effort (LE). LE provides an easy way to compare and select circuit topologies, choose the best number of stages for path and estimate path delay. The proposal of Particle Swarm Optimization (PSO) with constriction factor (PSO-CF) and mutative variants (PSO-M) presented in this thesis attempts to create an automated process of transistor sizing optimization. The method attempts to get the target circuit delay on tested circuit's critical path based on LE calculation that accepts generated transistor size by both PSO variants as inputs to fitness function. The optimization of the transistor size will stop if maximum iteration reached of different between PSO's found delay and objective delay is very small (near or similar to c0'). Various parameters, such as swarm size and iterations were tested under different initial positions to verify PSO's performance on a adder circuits namely modified half-adder (M-HA), modified full-adder (M-FA) and modified ripple-carry adder (MRCA). The experiments reported in this thesis showed that both PSO variants were efficient to automatically find the optimum transistor size with solution range of [1(T2,1(T15] for PSO-CF and [10°, 1(T16] for PSO-M.
format Thesis
author Johari, Muhammad Aiman
author_facet Johari, Muhammad Aiman
author_sort Johari, Muhammad Aiman
title Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari
title_short Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari
title_full Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari
title_fullStr Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari
title_full_unstemmed Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari
title_sort logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / muhammad aiman johari
publishDate 2015
url http://ir.uitm.edu.my/id/eprint/21626/1/TM_MUHAMMAD%20AIMAN%20JOHARI%20EE%2015_5.pdf
http://ir.uitm.edu.my/id/eprint/21626/
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