Design and simulation of serial peripheral interface core with APB interfacing / Muhammad Hafeez Sabparie ... [et al.]

• Main Authors: Sabparie, Muhammad Hafeez, Noorsal, Emillia, Sulaiman, Suhana, Saparon, Azilah
• Format: Article
• Language: English
• Published: Universiti Teknologi MARA 2021
• Subjects: Electric power distribution. Electric power transmission; Applications of electric power; Electric apparatus and materials. Electric circuits. Electric networks
• Online Access: https://ir.uitm.edu.my/id/eprint/52072/1/52072.pdf; https://ir.uitm.edu.my/id/eprint/52072/; https://jeesr.uitm.edu.my/
• Institution: Universiti Teknologi Mara

The model and design of the IP core of Serial Peripheral Interface (SPI) with Advanced Peripheral Bus (APB) interfacing is presented in this paper. SPI is known as a kind of serial protocol for serial communication bus developed by Motorola and has become de facto standard. There is possibility for a system to have more than one slaves for the integrated circuit, however the master can only be one at any given time. Hence, in this work, the SPI was modelled by Verilog code and it was simulated and synthesized using ModelSim and Quartus Prime Lite Edition 16.0 for earlier stage of design. While Synopsys Tools i.e. Design Compiler was used as the primary synthesis for the design. The SPI interface was designed to send or receive data from a single slave and efficient APB-SPI controller with flexible data width and frequency is proven for maximum frequency of 16 MHz. The modes of SPI also play its role in this work where this protocol can run through four modes that corresponds to four possible clocking configurations. The results showed that the core of SPI was successfully modelled for mode 0, 1, 2 and 3. In additon, the modes were simulated with maximum operating frequency of 16 MHz and flexibility in all four clocking modes. The ASIC design of this work consumed 27750 μm2 and 47.12μW using Silterra 0.18μm CMOS process.