Designing a phase-locked loop for a weather satellite image receiver / Siti Najihah Mohd Yusof
This thesis presents design of a phase-locked loop (PLL) at operating frequencies from 46 MHz to 48 MHz for a weather satellite image receiver. The main objective of the designed PLL is to assist the receiver system to track a radio frequency (RF) signal transmitted from the National Oceanic and Atm...
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| Format: | Thesis |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/68994/1/68994.pdf https://ir.uitm.edu.my/id/eprint/68994/ |
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| Institution: | Universiti Teknologi Mara |
| Language: | English |
| Summary: | This thesis presents design of a phase-locked loop (PLL) at operating frequencies from 46 MHz to 48 MHz for a weather satellite image receiver. The main objective of the designed PLL is to assist the receiver system to track a radio frequency (RF) signal transmitted from the National Oceanic and Atmospheric Administration (NOAA) satellite which has been down-converted to frequency modulation (FM) frequency 90.7 MHz. The PLL is part of a low cost ground receiving system for Automatic Picture Transmission (APT) image reception. The PLL software was designed and compiled using CCS C compiler and used Peripheral Interface Controller 16F84A (PIC16F84A) as the microcontroller while the PLL hardware was designed and then fabricated on a printed circuit board (PCB) using Protel DXP 2004. The PCB design layout for the PLL was also constructed by using Protel DXP 2004. For the practical testing of the PLL a 12V DC supply, a 9V DC supply and a spectrum analyzer are used to verify the functionality of the designed PLL. From the measurement, the PLL is recorded to operate at the desired frequencies. |
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