Evaluating and implementing noise tolerance precharge in full adder / Mohd Shamian Zainal, Shipun Anuar Hamzah and Azmi Sidek
The semiconductor device now day are dealing with the Very Large Scale Integrated (VLSI) circuit for performing the component such as logic, adder, multiplexer and other device. But in order to function in normal condition or in high speed condition the output node of the circuit are influence by th...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2006
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/81938/1/81938.PDF https://ir.uitm.edu.my/id/eprint/81938/ |
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| Institution: | Universiti Teknologi Mara |
| Language: | English |
| Summary: | The semiconductor device now day are dealing with the Very Large Scale Integrated (VLSI) circuit for performing the component such as logic, adder, multiplexer and other device. But in order to function in normal condition or in high speed condition the output node of the circuit are influence by the several type of noise in deep submicron circuit. The noise will cause the circuit produce the error output. To overcome this problem, one technique has been used. The technique is Noise Tolerance Precharge circuit design. In this paper the Noise Tolerance Precharge circuit will be combining into the Complemenry Metal Oxide Semiconductor (CMOS) circuit. The comparison for each result show the Noise Tolerance Precharge circuit output is more noise-immune and display batter result. The implemented circuits with Noise Tolerance Precharge result show the circuit is reduce noise 90% of the error in normal domino technique. The designs in this paper are based on MOS 0.35µ technology. |
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