Implementation and analysis of a 15-Level inverter topology With reduced switch count
Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been p...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Published: |
Institute of Electrical and Electronics Engineers
2021
|
| Subjects: | |
| Online Access: | http://eprints.um.edu.my/27955/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Universiti Malaya |